1. Field of the Invention
The present invention relates generally to a semiconductor memory device and particularly to a semiconductor memory device composed of an SRAM (static random access memory).
2. Description of the Related Art
SGT (surrounding gate transistor) technologies are known as measures for attaining higher levels of integration and performance in semiconductor devices (disclosed for example in Unexamined Japanese Patent Application KOKAI Publication Nos. H2-188966 and H7-99311). SGTs are vertical gate transistors in which a columnar semiconductor layer is formed on the surface of a semiconductor substrate and a gate is formed on the sidewall of the columnar semiconductor layer to surround it. In an SGT, the drain, gate, and source are arranged in the vertical direction. Therefore, the SGT has a significantly reduced occupying area compared with conventional planar transistors.
With the increasingly strong demands in recent years for large capacity SRAMs installed in LSIs (large-scale integrated circuits), it is desired to realize an SRAM having a small cell area with the use of SGTs.
FIG. 19A is a plane view of a CMOS 6T-SRAM memory cell composed of six SGTs, which is shown in an embodiment of Unexamined Japanese Patent Application KOKAI Publication No. H7-99311 and FIG. 19B is a cross-sectional view at A-A′ in FIG. 19A. In these figures, bit lines (801a, 801b) are formed by an n+ diffusion layer, a ground potential wire GND is formed by an n+ diffusion layer 802, and a power supply potential wire Vcc is formed by a p+ diffusion layer 803.
Columnar silicon layers composing access transistors (810a, 810b) for accessing the memory cell, driver transistors (811a, 811b) for driving the memory cell, and load transistors (812a, 812b) for supplying charge to the memory cell, respectively, are formed on these diffusion layers. Gates (804a, 804b, 804c, 804d) are formed around the columnar silicon layers. Memory nodes are composed of wiring layers (807a, 807b).
In the above memory cell (SRAM cell), the transistors each have the source, gate, and drain arranged vertically on the columnar silicon layer. Therefore, a small SRAM cell can be designed.
The above SRAM cell can attain a small cell area when the power supply potential wire 803 and ground potential wire 802 have approximately the minimum dimensions. However, the power supply potential wire 803 and ground potential wire 802 are formed by a p+ diffusion layer and an n+ diffusion layer, respectively. Therefore, they have significantly high resistance and it is difficult to achieve high SRAM operation speeds when they have approximately the minimum dimensions. On the other hand, when the power supply potential wire 803 and ground potential wire 802 are increased in dimension for high SRAM operation speeds, the SRAM cell has a larger area.
In SRAMs using conventional planar transistors, the power supply potential wire and ground potential wire are formed by low resistant Cu wires. Therefore, it is essential to form the power supply potential wire and ground potential wire by Cu wires in order for SRAMs using SGTs to achieve operation speeds equivalent to those of SRAMs using planar transistors.
Loadless 4T-SRAMs have been proposed as an SRAM having an SRAM cell area smaller than CMOS 6T-SRAMs (disclosed for example in Unexamined Japanese Patent Application KOKAI Publication No. 2000-12705). FIG. 1 shows an equivalent circuit to a memory cell of the loadless 4T-SRAM. This SRAM cell is composed of a total of four transistors: two PMOS access transistors (Qp11, Qp21) for accessing the memory and two NMOS driver transistors (Qn11, Qn21) for driving the memory.
Data holding operation in the case wherein data “L” is stored in a memory node Qa1 and data “H” is stored in a memory node Qb1 will be described hereafter as an example of operation of the memory cell in FIG. 1. A word line WL1 and bit lines BL1 and BLB1 all have a potential “H” while data is held. The threshold of the access transistors (Qp11, Qp21) is lower than the threshold of the driver transistors (Qn11, Qn21). The off-leak current of the access transistors (Qp11, Qp21) is, for example, approximately 10 to 1000 times larger in average than the off-leak current of the driver transistors (Qn11, Qn21). Therefore, the level “H” of the memory node Qb1 is held by an off-leak current running from the bit line BLB1 to the memory node Qb1 via the access transistor Qp21. On the other hand, the level “L” of the memory node Qa1 is stably held by the driver transistor Qn11.
The above loadless 4T-SRAM can attain a smaller SRAM cell area than CMOS 6T-SRAMs even with the use of SGTs.